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Home Page of the ILC DEPFET Collaboration

Charles University Prague MPI Halbleiterlabor IFIC Valencia Uni Karlsruhe
Uni Heidelberg RWTH Aachen Silicon Lab Uni Bonn MPI Muenchen

The International Linear Collider is a proposed new electron-positron collider. Together with the Large Hadron Collider at CERN , it would allow physicists to explore energy regions beyond the reach of today's accelerators. At these energies, researchers anticipate significant discoveries that will lead to a radically new understanding of what the universe is made of and how it works. The nature of the ILC's electron-positron collisions would give it the capability to answer compelling questions that discoveries at the LHC will raise, from the identity of dark matter to the existence of extra dimensions. In the ILC's design, two facing linear accelerators, each 20 kilometers long, hurl beams of electrons and positrons toward each other at nearly the speed of light. Each beam contains ten billion electrons or positrons compressed to a minuscule three-nanometer thickness. As the particles speed down the collider, superconducting accelerating cavities give them more and more energy. They meet in an intense crossfire of collisions. The energy of the ILC's beam can be adjusted to home in on processes of interest.

Fig. 1: Artist's view of an electron-positron collision and the futuristic drawing of the international linear collider. The electron-positron linear accelerator with its main tunnel is accompanied with a smaller service tunnel for the klystron. Total length of the tunnels are expected to be about 40km. (Source: www.linearcollider.org)

The vertex detector at this future linear e+e- collider will be a set of cylindrical detectors arranged in ladders around the interaction point. Each ladder is an array of pixel cells read out at the end of the ladder outside the senstive volume. We are proposing an active pixel sensor array with a DEPFET as the pixel cell. In order to minimize the multiple scattering contributions to the impact parameter resolution the reduction of any material in the detector area to a minimum is mandatory. Both the material needed for cooling and supports of the sensors and the sensor material itself have to be minimized. The row-wise read out of the DEPFET array with only one row being active a time reduces the power consumption in the sensitive area to about 1W for the entire vertex detector and therefore the effort and material needed for cooling. Our concept for thin DEPFET arrays can be seen in Fig. 2. The DEPFET pixel array is made on thin (50μm in this study) detector grade silicon supported by a directly bonded silicon frame of ≈300 μm thickness. The read-out electronics, the lines for power, slow control, and data transmission are placed at both short sides of the ladder outside the sensitive volume of the vertex detector; the thinned steering chips (also 50 μm) for the row-wise read-out are attached on the thick frame along the long side of the ladder. The read-out circuits at the ends may be attached to cooling blocks outside the sensitive volume of the vertex detector, if needed.

Fig. 2: Module concept for the vertex detector at the International Linear Collider (ILC) and mechanical samples of thinned silicon modules (50μm) supported by a thicker frame of silicon.

A new generation of DEPFET active pixel sensors with 25μm pixel size was developed at the MPI Semiconductor Laboratory to meet the requirements in the point measurement resolution and multiple track separation. A new technology with two metal and two poly-silicon conducting layers has been established at the HLL for the production of prototype arrays. The produced DEPFETs show the expected and previously simulated behavior. Moreover, a new technology for thin semiconductor sensors with electrically active back side based on direct wafer bonding and deep wet etching was invented at the laboratory. The feasibility of this approach was shown with the production of 50μm thin PiN diodes of various areas up to 6.5cm2. The dominant background of pair-produced electrons which penetrate the inner layer of the vertex detector at the ILC imposes a requirement on radiation hardness of about 100krad for a 5 year life time. In addition there is NIEL (Non Ionizing Energy Loss) damage due to the neutron background which is estimated to be at the level of 109 1MeV-neutrons/cm2 per year. Since there is no charge transfer during operation of DEPFET matrices, damage of the silicon bulk due to NIEL is of minor importance for this kind of devices. However, all MOS devices are inherently susceptible to ionizing radiation. The main total ionizing dose effects are the shift of the threshold voltage to more negative values caused by radiation induced charge build up in the oxide and interfacial regions, build up of states at the interface between Si and SiO2 resulting in an increased sub-threshold slope and possibly a higher 1/f noise, and the reduction of the transconductance due to a lower mobility of the charge carriers in the channel after irradiation. MOS-type DEPFETs have been irradiated with up to 1Mrad with a 60Co source and show even after this severe damage still a good spectroscopic performance (see Fig. 3).

Fig. 3: 55Fe spectrum taken with a linear MOS-type DEPFET in drain current read out at room temperature after irradiation with a total ionizing dose of 1 Mrad(Si). The inset shows the noise peak with an ENC(rms)=3.5e-.

The high occupancy in the first layer of the ILC vertex detector, caused by the beamstrahlung, has to be suppressed by a very fast read-out cycle of about 50MHz. In collaboration with the Universities Bonn and Mannheim a read-out concept for a DEPFET pixel based vertex detector facing these high speed requirements has been developed. The proposed concept is completely based on current mode techniques well suited to the operation mode of the DEPFET sensor. A prototype hybrid housing the steering chip for the row-wise read out (SWITCHER) and the front-end chip (CURO - CUrrent Read Out) is shown in Fig. 4. These hybrids were tested in the lab and in the 6GeV testbeam of the DESY synchrotron. The achieved signal/noise ratio is about 125 with DEPFET matrices of 450 μm thickness. This high S/N ratio has to be scaled by a factor of 9 as the matrices for the ILC have to be 50 μm thin. The main noise contribution was due to system cross-talk and pickup, which can be reduced by improvement of the readout system. We expect with the new system about 100 electrons (ENC) noise, which would give an excellent S/N ration of about 40 for 50μm thick matrices read out at full ILC speed.

Fig. 4: Prototype module with the 64x128 pixel DEPFET matrix in the center, the SWITCHER chips to the left and the right, and the CURO readout chip at the bottom (left), and Landau distribution of 6GeV electrons at the DESY testbeam facility (right).

For more information please click on the components below



Switcher Thinning Technology Radiation Tolerance Beam Test CURO The ILC Vertex Detector based on DEPFETs
ILC Project


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Topic revision: r7 - 2008-01-17 - PeterFischer
 
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